1. Field of Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a nonvolatile (e.g., flash) memory device and a method for fabricating the same capable of improving the device characteristic.
2. Description of Related Art
Generally, an EEPROM device stores a bit or multi-bit using a single cell, and is a memory device capable of electrically programming and erasing data.
Meanwhile, among EEPROM devices, a FLOTOX type EEPROM uses hot electrons derived from the high voltage for the programming operation, and uses F-N (Fowler-Nordheim) tunneling for the erasing operation. Such an EEPROM device includes a floating gate electrode formed on upper part of a tunnel oxide layer, and a control gate electrode formed on the floating gate electrode to receive a predetermined voltage.
Such a conventional EEPROM device is classified into a single poly EEPROM and a double poly EEPROM according to a manufacturing process and the number of the used polysilicon layers.
Hereinafter, the method for fabricating the single poly EEPROM device will be explained with reference to accompanying drawings.
FIG. 1 is a sectional view representing a conventional EEPROM device.
First, a substrate on which, the first type, for instance, a p type-well is defined is prepared.
Then, an isolation area 11 is formed by filling a predetermined area of the substrate with an insulating layer 17 through a LOCOS (Local Oxidation of Silicon) process or an STI (Shallow Trench Isolation) process.
Then, a junction area 12 is formed by implanting the second ions, for instance, n+ ions using a mask onto a predetermined area of an active area positioned between the isolation areas 11.
After that, the mask used in the ion implantation is removed, and the substrate 10 is heat-treated so that ions implanted onto the junction area 12 are activated.
Then, a gate insulating layer 13 is deposited on the substrate 10 including the junction area 12.
Then, a predetermined area of the gate insulating layer 13 is wet-etched so that the thickness of the gate insulating layer 13 is reduced. At this time, the oxide layer with the thickness partially reduced is called a tunnel oxide layer 14.
Then, polysilicon is deposited on the gate insulating layer 13 including the tunnel oxide layer 14, and is selectively removed, thereby forming a floating gate 15a. At this time, the floating gate 15a is formed so as to cover the tunnel oxide layer 14. An activated transistor gate 15b is formed simultaneously with the floating gate 15a through the etching process for forming the floating gate 15a. 
Then, the second type, for instance, n type ions are implanted onto the floating gate 15a and the activated transistor gate 15b. 
However, the method for fabricating the conventional EEPROM device uses an independently-buried junction area for an erase mechanism control, and the conventional EEPROM device should be made considerably in a large size to increase the voltage level coupled to the floating gate. Such a structure makes it difficult to reduce the size of the cell.
In addition, since the erase mechanism is performed only by a positive method, a high voltage is applied to the junction area in the programming and erasing operations, so that the junction area having a withstanding voltage against the voltage drop due to a leakage and a high BV (Breakdown Voltage) voltage is needed. This is inadvantageous when making the device with a size below a predetermined level.